The invention relates generally to a thin film transistor and more particularly to a thin film transistor in which the parasitic capacitance does not vary with the relative positioning of the thin film transistor elements. Thin film transistors (TFT's) formed in accordance with the invention are advantageously included in active matrix liquid crystal displays, image sensors and three dimensional integrated circuits which require uniform TFT characteristics.
A conventional thin film transistor 230 having the structure discussed in Japan Display '86, 1986, pp. 196-199 is show generally in FIGS. 3 and 4. A source electrode 202 and a drain electrode 203 are formed on an insulating substrate 201, made of glass, quartz or sapphire. Source 202 and drain 203 are formed of polycrystal silicon thin films that include impurities, such as donors or acceptors. A source line 204 and a drain line 205 are disposed on substrate 201 in contact with source electrode 202 and drain electrode 203, respectively. A channel region 206, formed of a thin film of polycrystal silicon, is disposed thereon to contact both source 202 and drain 203. A gate insulating film 207 covers these elements and a gate electrode 208 is disposed thereon, patterned to oppose channel 206 with insulating film 207 therebetween.
Conventional thin film transistors formed as in FIGS. 3 and 4 have disadvantages as illustrated in the plan views in FIGS. 5A, 5B and 5C and in the equivalent circuit of the FIG. 6. A TFT 350a, 350b and 350c shown in FIGS. 5A, 5B and 5C respectively, include a source 301 and a drain 302 formed on an insulating substrate and a channel 303 therebetween. These elements are covered with a gate insulating film 307. A gate electrode 304 is patterned on gate insulating film 307 and overlaps portions of source 301, channel 303 and drain 302. Parasitic capacitance 40 is generated by the portion of gate electrode 304 overlapping source 301 and channel 303 corresponding to similarly cross-hatched region S.sub.1. Parasitic capacitance 402 is generated by a portion of gate electrode 304 opposing a portion of channel 303 and drain 302 corresponding to similarly cross-hatched region S.sub.2.
If the pattern of gate electrode 304 is unintentionally displaced in the direction of an arrow 305, parasitic capacitance 401(S.sub.1) is decreased and parasitic capacitance 402(S.sub.2) is increased. Conversely, if the pattern of gate electrode 304 is unintentionally displaced in the direction of an arrow 306, parasitic capacitance 401(S.sub.1) is increased and parasitic capacitance 402(S.sub.2) is decreased. Accordingly, the parasitic capacitance of the thin film transistor varies widely with pattern slippage of gate electrode 304 towards either source 301 or drain 302.
Major factors contributing to such pattern slippage are alignment slippage of gate electrode 304 and pitch slippage between photo masks. Consequently, the parasitic capacitance can unintentionally vary within the same substrate or between different substrates making it difficult to maintain the circuit at a constant predetermined level.
If the thin film transistor is included within a liquid crystal display, individual display element properties will likewise vary which adversely affects picture quality. Occurrences or pattern slippage increase with the size of liquid crystal displays so that there is substantial display quality deterioration in large LCD's. Picture element variation caused by pattern slippage has been a major obstacle to forming large LCD's.
These variations in capacitance also cause problems when conventional TFT's are included in image sensors and three dimensional integrated circuits because it is difficult to maintain the circuits at constant predetermined levels, a major obstacle for practical use.
Accordingly, it is desirable to develop an improved TFT which does not have shortcomings associated with variations in parasitic capacitance occurring in conventional TFT's.